VHDL Programming

(C. Jardin) #1

336 Chapter Fourteen


In the counter example, the first value read is the clksignal. The Tex-
tIOstatement reads a STD_LOGICvalue from line l and assigns the value
readto variable tmpclk. Later, the tmpclkvariable is assigned to the
signal clk.
The process continues to read a line, read a time value, wait until that
time value occurs, read all vector values, and apply vector values until the
end of the file is reached. When the end of the file is reached, the loop
terminates, an assertion message is written to standard output, and the
process waits forever. The WAITstatement after the assertion at the end
of the loop doesn’t have a termination condition and, therefore, waits
forever, effectively stopping execution of this process.
The TEXTIOreadline statement inside the whileloop reads a vector line
from a vector file. Following is an example vector file:

--- vector file for counter
-- time clk ld up_dwn clk_en din
10 0001 0
20 1101 50
30 0001 0
40 1001 0
50 0001 0
60 1001 0
70 0001 0
80 1001 0
90 0001 0
100 1101 10
110 0001 0
120 1001 0
130 0001 0
140 1001 0
150 0001 0
160 1001 0

The first two lines of the vector file do not start with valid numbers and
are treated as comment lines. Comment lines can be embedded anywhere
in the file. Comments can also be placed at the end of a vector because
any data after the last field of the vector are ignored.
Each vector line starts with a time value and then contains a string of
values to be assigned to the DUT at that time. Spaces can be embedded
between vector values if a corresponding read function exists in the while
loop to skip the space.
For the stimulus only testbench, the test process reads a vector from
the file and applies the stimulus to the DUT. The stimulus only testbench
does not check the output results of the DUT in reaction to the applied
stimulus. The stimulus only testbench is most useful for a quick check of
a piece of a design that is easy for the designer to verify manually or for
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