CPU: RTL Simulation 339
read(l, space); --- skip a space-- read din value
read(l, tmpdin, good_val);
assert good_val REPORT “bad din value”;read(l, space); --- skip a space---- the difference in the file is below-- read good output value
read(l, tmpqout, good_val);
assert good_val REPORT “bad qout value”;-- Compare outputs
assert tmpqout = qout REPORT “vector mismatch”;clk <= tmpclk;
ld <= tmpld;
up_dwn <= tmpup_dwn;
clk_en <= tmpclk_en;
din <= tmpdin;END LOOP;
ASSERT false REPORT “Test complete”;
WAIT;
END PROCESS;
END full;The full testbench looks exactly the same as the stimulus only test-
bench for most of the file. The full testbench has a top-level entity with
no ports, an architecture that instantiates the DUT, and awhileloop that
reads a vector file. The differences are in thewhileloop itself. The first
part of thewhileloop is exactly the same. The process reads a time value
and waits for that time value to occur. The full testbench is different inthat,
not only does the full testbench read the input values, but it also reads the
output values and then performs a compare operation between the output
values from the DUT versus the values read from the file. If a mismatch
is found, an assertion message is generated to let the designer know that
the output results did not match the known good results.
The full testbench also reads from a vector file to get the stimulus for
the design and the expected results. The vector file contains a time value,
the input values, and the expected output values. Following is the full
testbench vector file:--- vector file for counter
-- time clk ld up_dwn clk_en din dout
0 0001 0 0
10 1001 0 255