VHDL Programming

CPU: RTL Simulation 341

-- setup the clock

force -repeat 20 clk 0 0, 1 10

-- log the results to a file

list *

-- setup initial signal conditions

force ld 0

force up_dwn 0

force clk_en 1

force din 16#00

-- run the simulation

run 100

--- set next signal conditions

force ld 1

force up_dwn 0

force clk_en 1

force din 16#AA

--- run the simulation

run 200

--- set next signal conditions

force ld 1

force up_dwn 0

force clk_en 1

force din 16#55

--- run the simulation

run 200

write list data.out

quit -f

The command language used for this testbench is the Model Technology

ModelSim command language. This simulator has a very rich command

language that allows the designer to perform all of the necessary operations

to compile designs, load designs, debug designs, save designs, and so on. The

ModelSim simulator also has the capability to generate repeating clock sig-

nals to drive the design. The first command in the testbench file creates a

repeating clock for signal clk. The clock repeats every 20 time units and is

set to a ‘ 0 ’value at time 0 and a ‘ 1 ’value at time 10.

The next command (list *) allows the designer to write all the signal

values to an output file. The *specifies that all signals be written to

the file.

The next few commands in the file set up stimulus values on the counter

input signals. The forcecommand sets the signal to a value until it is