VHDL Programming

346 Chapter Fourteen

USE WORK.count_types.all;

ARCHITECTURE fast OF testbench IS

-----------------------------------

-- component declaration for counter

-----------------------------------

COMPONENT count

PORT (clk : IN std_logic;

ld : IN std_logic;

up_dwn : IN std_logic;

clk_en : IN std_logic;

din : IN bit8;

qout : INOUT bit8);

END COMPONENT;

SIGNAL clk, ld, up_dwn, clk_en : std_logic := ‘ 0 ’;

SIGNAL qout, din : bit8;

BEGIN

-- instantiate the component

uut: count

PORT MAP(clk => clk,

ld => ld,

up_dwn => up_dwn,

clk_en => clk_en,

din => din,

qout => qout);

-- generate the clock in the testbench

clk <= not clk after 10 ns;

-- provide stimulus and check the result

test: PROCESS

TYPE stim_vec is

RECORD

event_time : time;

ld : std_logic;

up_dwn : std_logic;

clk_en : std_logic;

din : bit8;

qout : bit8;

END RECORD;

TYPE vec_array is array(0 to 8) of stim_vec;

VARIABLE stim_array : vec_array := (

(0 ns, ‘ 0 ’, ‘ 0 ’, ‘ 1 ’, 10, 10),

(20 ns, ‘ 1 ’, ‘ 0 ’, ‘ 1 ’, 100, 2),

(30 ns, ‘ 0 ’, ‘ 0 ’, ‘ 1 ’, 0, 0),

(100 ns, ‘ 1 ’, ‘ 0 ’, ‘ 1 ’, 55, 8),

(110 ns, ‘ 0 ’, ‘ 0 ’, ‘ 1 ’, 0, 0),

(150 ns, ‘ 1 ’, ‘ 0 ’, ‘ 1 ’, 150, 58),

(160 ns, ‘ 0 ’, ‘ 0 ’, ‘ 1 ’, 0, 151),