VHDL Programming

(C. Jardin) #1
is small enough, removing the hierarchy will create a smaller and faster
design. Finally IO pads will not be added to the design as the Altera place
and route tool will do this automatically. The optimize user interface with
all the switches set is shown in Figure 15-8. Selection of the Optimize
button will perform the optimization process and implement the specified
design with Apex 20KE technology primitives.
The Report tab is used to generate area and timing reports. An area
report gives the size of the design based on the design implementation
in the target technology. To generate a report, select the Report Area

362 Chapter Fifteen


Figure 15-6
Set Order of Input
Files.

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