VHDL Programming

button as shown in Figure 15-9. The report generated will look like the

one shown below:

->report_area -cell_usage -all_leafs

*******************************************************

Cell: cpu View: rtl Library: work

cpu

*******************************************************

Cell Library References Total Area

GND apex20e 1 x 1 1 GND

CPU Design: Synthesis Results 363

Figure 15-7
Set Clock Constraint
to 30 Mhz.