VHDL Programming

Number of nets : 198

Number of instances : 61

Number of references to this view: 0

total accumulated area:

DELAY flex10 8 x

Number of GND : 8

Number of LCs : 398

Number of Memory Bits : 512

Number of TRIs : 16

Number of VCC : 1

Number of SHIFT : 1

Number of accumulated instances : 443

***********************************************

Device Utilization for EP20K200EFC484

***********************************************

Resource Used Avail Utilization

-----------------------------------------------

IOs 37 376 9.84%

LCs 398 8320 4.78%

Memory Bits 512 106496 0.48%

-----------------------------------------------

Info, Command 'report_area' finished successfully

The last step in the synthesis process is to write out a gate-level

description for the optimized design. For this example the output format

used will be EDIF. The common term for this output file is a netlist,

because it describes the primitives used in the design and the signals (or

nets—short for networks) used to connect these primitives. To generate the

netlist select the Output tab, modify the name of the output file as neces-

sary, and then select the Write button. This is shown in Figure 15-10.

This netlist will now be passed to the Altera place and route tools to

create the actual implementation of the device. This process is described

in the next chapter.

SUMMARY

In this chapter, we synthesized all of the VHDL RTL descriptions of the

CPU and analyzed the results. In the next chapter, we read the synthesized

netlist into the place and route tools, and run the place and route to imple-

ment the design in the target technology.

366 Chapter Fifteen