VHDL Programming

reg work 1 x 11 11 LCs

1 1 GND

reg work 1 x 16 16 LCs

1 1 GND

regarray_notri work 1 x 1 1 VCC

128 128 Memory Bits

shift work 1 x 1 1 shift

trireg_notri work 3 x 16 48 LCs

1 3 GND

Number of ports : 37

CPU Design: Synthesis Results 365

Figure 15-9
Report Area.