VHDL Programming

Place and Route 371

RAM. The place and route tool generates the RAM image to be loaded into

the RAM on the device.

The routing channels contain vertical and horizontal lines. The hori-

zontal wires connect devices within a row, while the vertical lines allow

connections across rows. Most routing channels contain wires of different

Logic

Block 1

Logic

Block 2

Logic

Block 3

1 1

1 1

Figure 16-3
Logic Block
Interconnection.

Logic

Area

Logic

Area

Logic

Area

Logic

Area

Logic

Area

Logic

Area

Logic

Area

Logic

Area

Logic

Area

Routing Channels

Figure 16-2

FPGA Chip

Architecture.