VHDL Programming

370 Chapter Sixteen

Place and Route Process

The place and route process places each macro from the synthesis netlist

into an available location on the target silicon and connects the macros

using routing resources available on the target silicon. The place and

route process is shown in Figure 16-1.

The synthesis netlist is input to the placement process. The placement

process analyzes all of the macros used in the design and their connectivity

to try to determine an optimal placement for the macros. The placement

algorithms take into account a number of technology-specific factors of the

target technology to determine whether a particular placement is good or

not. After a trial placement and signal route is attempted, the design is

analyzed with respect to timing constraints. If the timing constraints are

not met, the place and route software continues to try different placements

and signal routing to try to meet the constraints.

Typical target devices have areas of the chip where logical functions

are placed, and areas where interconnect signals are routed to connect the

logical functions. This is shown in Figure 16-2.

The device is split into a number of logic areas with routing channels

that surround the logic areas. Logic areas contain the logical gates to

implement the boolean function of the design. Routing channels contain

the signals that are used to connect the logical gates together. For FPGA

devices, the routing channels contain programmable interconnect wires.

FPGA devices use an onboard RAM to store the value of programmable

switches that are used to form the signal interconnections. By enabling

the proper sets of pass transistor gates, signal interconnections between

logic gates can be formed as shown in the example in Figure 16-3.

To make a connection from logic block 1 to logic block 3, all of the

switches shown need to be enabled with a logic 1 value. The logic gates of

the devices are connected to local routing signals that can be connected

to more global routing signals by pass transistors that bridge the two

signals. The control signals of the pass transistors are stored in a loadable

Constraints

Met?

Synthesis

Netlist

Placement Routing

Yes

Figure 16-1 No
Place and Route
Process.