in2, and pin-to-pin delays from input in1to output yand from input in2
to output y.
Following is the VITAL model that implements the functionality of the
AND2device:----- CELL AND2 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
library alt_vtl;
use alt_vtl.SUPPORT.all;-- entity declaration --
entity AND2 is
generic(
TimingChecksOn: Boolean := True;
XGenerationOn: Boolean := False;
InstancePath: STRING := “*”;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of AND2 : entity is TRUE;
end AND2;-- architecture body --
architecture AltVITAL of AND2 is
attribute VITAL_LEVEL1 of AltVITAL : architecture is
TRUE;SIGNAL IN1_ipd : STD_ULOGIC := ‘U’;
SIGNAL IN2_ipd : STD_ULOGIC := ‘U’;begin---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)384 Chapter Seventeen