VHDL Programming

Attribute VitalLevel1specifies that the VITAL model is level 1

compliant. Level 1 models are modeled only with VITAL primitives and

can be accelerated. Some simulators have compliance checkers that can

validate level 1 compliance.

The architecture contains a block labeled WireDelaywhich contains

the VHDL description that actually delays the input signals. The block

contains a call to the VitalWireDelayprocedure for each input port. The

VitalWireDelayprocedure delays the input ports by the value passed to

the appropriate generic used in the procedure call. In this example,

generic tipd_in1is used to delay input in1, and generic tipd_in2is used

to delay input in2.

After the wire delay section is the timing check section. This example has

no timing check section because it is a purely combinational gate model.

The next section is the functionality section. This section contains the

statements that model the behavior of the device. This section starts with

a process labeled VitalBehavior. Notice that the process is sensitive to

the delayed versions of the two input signals,in1_ipdand in2_ipd. There

are a number of local variables declared and a statement that performs

an ANDfunction of the two inputs. This ANDfunction can be built into the

simulator so that execution can be accelerated.

The last section of the architecture starts with the VitalPathDelay

procedure call. This section is the path delay section. This section schedules

the new logic values calculated in the functionality section to occur after

the appropriate delay. This section consists of a VitalPathDelay01proce-

dure call for each output from the entity.

CPU:Vital Simulation 387

U1

U2

U3

8 ns

8 ns

Figure 17-4

Wire Delay

Representation.