The first thing to notice about this model is that there are quite a few
more generics used to pass timing information to the model. This is
because this model has more input ports; therefore, there are more input
delay generics and the model contains timing checks that need timing
information passed to them.
The wire delay section now delays four input ports instead of two. The D,
CLRN,PRN, and CLKinputs are delayed in the wire delay section. The archi-
tecture for the DFFalso contains a number of local signals and variables used
to hold intermediate values for the timing check and functionality sections.
The final declaration item in the architecture declaration section is a table
that is used to model the behavior of the DFF. This DFFmodel uses a VITAL
State Table procedure to model the behavior of the device. This table is used
in the functionality section of the model by the VitalStateTableprocedure
call. The signal values of the signals passed to the VitalStateTableproce-
dure call are compared to the values in the table, and the new values for the
output signals and next state are predicted.
The timing check section for this example contains a VitalSetupHold-
Checkprocedure call. This procedure checks the setup and hold of data
changes versus the clock for the DFFdevice. The violation signal returned
by the VitalSetupHoldCheckprocedure is used to affect the behavior of
the DFF device by the fact that its value is passed to the VitalStateTable
that controls the behavior of the DFFdevice.
The functionality section of the DFFdevice contains the single call to the
VitalStateTableprocedure to calculate the value of the Qoutput based on
the values of the input ports, the previous state, and the violation signal
from the timing check procedures. Based on all of these inputs, a table row
matches, and the new Qoutput is passed to the path delay section.
The path delay section looks very similar to the path delay section for
the AND2device discussed previously. The path delay section contains a
single call to the VitalPathDelay01procedure, which schedules output Q
with the appropriate delay value.
To see how all of these VITAL functions and procedures are imple-
mented, look at the VITAL packages included on the CD with the book or
visit http://www.vhdl.org/vital.SDF File
The other piece of functionality needed to complete the VITAL simulation
picture is the SDF back-annotation file. This file is generated by the place392 Chapter Seventeen