VHDL Programming

CheckEnabled => TO_X01(( (NOT PRN_ipd)

) OR ( (NOT

CLRN_ipd) ) ) /= ‘ 1 ’,

RefTransition => ‘/’,

HeaderMsg => InstancePath & “/DFF”,

XOn => DefTimingXon,

MsgOn => DefTimingMsgon );

end if;

-------------------------

-- Functionality Section

-------------------------

Violation := Tviol_D_CLK;

VitalStateTable(

StateTable => DFF_Q_tab,

DataIn => (

Violation, CLRN_ipd, CLK_delayed,

D_delayed, PRN_ipd, CLK_ipd),

Result => Results,

NumStates => 1,

PreviousDataIn => PrevData_Q);

D_delayed := D_ipd;

CLK_delayed := CLK_ipd;

----------------------

-- Path Delay Section

----------------------

VitalPathDelay01 (

OutSignal => Q,

OutSignalName => “Q”,

OutTemp => Results(1),

Paths => (0 => (PRN_ipd’last_event,

tpd_PRN_Q_negedge, TRUE),

1 => (CLRN_ipd’last_event,

tpd_CLRN_Q_negedge, TRUE),

2 => (CLK_ipd’last_event,

tpd_CLK_Q_posedge, TRUE),

3 => (D_ipd’last_event,

tpd_CLK_Q_posedge, TRUE)),

GlitchData => Q_VitalGlitchData,

Mode => DefGlitchMode,

XOn => DefGlitchXOn);

end process;

end AltVITAL;

configuration CFG_DFF_VITAL of DFF is

for AltVITAL

end for;

end CFG_DFF_VITAL;

CPU:Vital Simulation 391