VHDL Programming

-- ready : IN std_logic;

-- reset : IN std_logic;

-- rw : OUT std_logic;

-- vma : OUT std_logic);

--END cpu;

ARCHITECTURE EPF10K10TC144_a3 OF cpu IS

SIGNAL gnd : std_logic := ‘ 0 ’;

SIGNAL vcc : std_logic := ‘ 1 ’;

SIGNAL ......

..........

To compile the VCOMPONENTSpackage into library alt_vtl, the follow-

ing commands are executed in ModelSim:

vlib alt_vtl

vcom -work alt_vtl alt_vtl.cmp

Because there are no other library declarations for the actual vital

library, the vital library entities need to be compiled into the working

library to be visible. Following is the command to perform this step:

vcom alt_vtl.vhd

After these two files have been compiled, the VITAL netlist can be com-

piled into the working library. The following command compiles the

netlist:

vcom cpuout.vhd

We still need to simulate design TOPto verify the gate-level imple-

mentation of the CPU. However, this time, the CPU RTL description is re-

placed with a VITAL description of the CPU. This can be accomplished

by two different methods. The first involves compilation order,and the

second is by direct specification. Remember that the last architecture

compiled is used by default for an entity. By compiling architecture

EPF10K10TC144_a3last, this architecture is used for entity cpu.

The other method is to write a configuration for architecture topthat

specifies exactly which architecture is to be used. The following example

shows two configuration statements for the two different implementations

of the CPU:

configuration topconrtl of top is

for behave

for U1 : cpu use entity work.cpu(behave);

end for;

CPU:Vital Simulation 395