Chapter 18 At Speed Debugging Techniques

Throughout the book so far we have discussed a number

of techniques for implementing VHDL designs and ways

to make sure that the VHDL designs behave as expected.

These techniques include simulation, synthesis of the

design to an FPGA or ASIC, and gate-level simulation

using VITAL libraries. A new technique called At-Speed

Debugging is just becoming available that allows much

higher performance verification than a typical simulator,

yet provides the design visibility necessary to properly

debug a design. This technique provides designers with

the ability to debug their design in the target system, at

target speed, at the VHDL RTL level.

Figure 18-1 shows a block diagram of how this works.

The VHDL for the device is read into a tool that auto-

matically creates and inserts a small debug core into the

device that probes internal signals. The debug core is cre-

ated based on information from the designer about what

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