VHDL Programming

signals are to be probed. This debug core communicates through the

JTAG port on the device to an HDL debugger executing on a host plat-

form. The HDL debugger sends and receives data from the debug core

and displays this data in context with the HDL for the design. Wave-

forms of the internal device data can also be displayed, providing the

ability to trace down problems in the design.

This technique works well for any design, but it works especially well

for designs where a tremendous amount of data must be processed by

the device to determine whether the device is working properly. For

instance, devices that process audio or video information require a

tremendous amount of data to be processed before it can be determined

that the device is working properly. A video processor might need to pro-

duce several minutes of high-quality video data to determine whether

the encryption decoding algorithm is working properly. Running at or

near speed will allow images to be generated quickly and the device

function to be analyzed for correctness.

The only system as of this writing that performs as described is the

Bridges2Silicon debugger from Bridges2Silicon. A block diagram of the

system is shown in Figure 18-2.

The Bridges2Silicon debugger contains two tools. The Bridges2Silicon

instrumentor reads the VHDL description and adds the debug core, called

an Intelligent In-Circuit Emulator (IICE) to the design. The Bridges2Silicon

debugger communicates with the JTAG port on the target device, reads

the database created by the instrumentor, and reads the original source

files created by the designer.

400 Chapter Eighteen

FPGA or

SOC

FPGA or

SOC

IICE

JTAG

Hardware System

HDL

Debugger

Figure 18-1
At-Speed Debugging
Overview.