VHDL Programming

Write Instrumented Design

Once all the signals and breakpoints have been instrumented, the instru-

mented design can be written out. This design will include the original

design tree plus the IICE core added for debugging. The IICE core will be

connected in such a way as to probe all the instrumented signals in the

design. Select the File Saveand Instrumentmenu items to write out the

instrumented design.

Implement New Design

The write instrumented design process will produce a new version of the

VHDL files for the CPU design. These files need to be synthesized as

described in earlier chapters. The output of the synthesis process is an

EDIF netlist. The EDIF netlist is placed and routed with the Altera

Quartus tools to produce a file that is programmed into the Altera device

At Speed Debugging Techniques 405

Figure 18-5
Top Level Unit and
Language Specified.