VHDL Programming

26 Chapter Two

Time Delta Activity

10 ns (1) A <= 0

evaluate inverter

(2) B <= 1

evaluate AND

evaluate NAND

(3) D <= 1

C <= 0

evaluate AND

(4) D <= 0

11 ns

Figure 2-8
Delta Delay Evalua-
tion Mechanism.

The inverter calculates the new value for signal B, which is the value ‘ 1 ’.

This value is not propagated immediately, but is scheduled for the next

delta time point (delta 2).

The simulator then begins execution of delta time point 2. Signal B is

updated to a ‘ 1 ’value, and the AND gate and NAND gate are reevaluated.

Both the AND gate and NAND gate now schedule their new values for

the next delta time point (delta 3).

When delta 3 occurs, signal D receives a ‘ 1 ’value, and signal C receives

a ‘ 0 ’value. Because signal C also drives the AND gate, the AND gate is

reevaluated and schedules its new output for delta time point 4.

To summarize, simulation deltas are an infinitesimal amount of time

used as a synchronization mechanism when 0 delay events are present.

Delta delay is used whenever 0 delay is specified, as shown in the fol-

lowing:

a <= b AFTER 0 ns;

Another case for using delta delay is when no delay is specified. For

example:

a <= b;

In both cases, whenever signal bchanges value from an event, signal

ahas a delta-delayed signal assignment to it.

An equivalent VHDL model of the circuit shown in Figure 2-6, except

for the flip-flop, is shown in the following: