VHDL Programming

Behavioral Modeling 25

AND First NAND First

evaluate inverter evaluate inverter

B <= 1 B <= 1

evaluate AND (C = 1) evaluate NAND

D <= 1 C <= 0

evaluate NAND evaluate AND

C <= 0 D <= 0

evaluate AND

D <= 0

Figure 2-7
Comparison of Two
Evaluation Mecha-
nisms.

The NAND gate reevaluates and calculates its new value as ‘ 0 ’. The

change on the output of the NAND gate causes the AND gate to reevaluate

again. The AND gate now sees the value of B, a ‘ 1 ’value, and the new

value of signal C, a ‘ 0 ’value. The AND gate now predicts a ‘ 0 ’on its

output. This process is summarized in Figure 2-7.

Both circuits arrive at the same value for signal D. However, when the

AND gate is evaluated first, a rising edge, one delta delay wide, occurs on

signal D. This rising edge can clock the flip-flop, depending on how the

flip-flop is modeled.

The point of this discussion is that without a delta synchronization

mechanism, the results of the simulation can depend on how the simulator

data structures are built. For instance, compiling the circuit the first time

might make the AND gate evaluate first, while compiling again might

make the NAND gate evaluate first—clearly not desirable results; simu-

lation deltas prevent this behavior from occurring.

The same circuit evaluated using the VHDL delta delay mechanism

would evaluate as shown in Figure 2-8.

The evaluation of the circuit does not depend on the order of evalua-

tion of the NAND gate or AND gate. The sequence in Figure 2-8 occurs

irrespective of the evaluation order of the AND or NAND gate.

During the first delta time point of time 10 nanoseconds, signal A receives

the value ‘ 0 ’. This causes the inverter to reevaluate with the new value.