436 Appendix B: VHDL Reference Tables
Table B-1
Continued.
Statement or Clause Example(s)Component Declaration COMPONENT component_name
PORT (port1_name : port1_type;
port2_name : port2_type;
port3_name : port3_type);
END COMPONENT;Component Instantiation instance_name : component_name PORT MAP
(first_port, second_port, third_port);
instance_name : component_name PORT MAP
(formal1 => actual1, formal2 => actual2);Conditional Signal Assignment target <= first_value WHEN (x = y) ELSE
second_value WHEN a >= b ELSE
third_value;Configuration Declaration CONFIGURATION configuration_name OF
entity_name IS
FOR architecture_name
FOR instance_name : entity_name USE
ENTITY
library_name.entity_name
(architecture_name);
END FOR;
FOR instance_name : entity_name USE
CONFIGURATION
library_name.configuration_name;
END FOR;
END FOR;
END configuration_name;Constant Declaration CONSTANT constant_name : constant_type :=
value;Entity Declaration ENTITY entity_name IS
PORT (port1 : port1_type;
port2 : port2_type);
END entity_name;Exit Statement EXIT;
EXIT WHEN a <= b;
EXIT loop_label WHEN x = z;File Type Declaration TYPE file_type_name IS FILE OF data_type;File Object Declaration FILE file_object_name : file_type_name IS IN
“/absolute/path/name”;For Loop FOR loop_variable IN start TO end LOOP
--do_some_stuff
END LOOP;