VHDL Programming

438 Appendix B: VHDL Reference Tables

Table B-1

Continued.

Statement or Clause Example(s)

Library Declaration LIBRARY library_name;

Loop Statement FOR loop_variable IN start TO end LOOP

--do lots of stuff

END LOOP;

WHILE x < y LOOP

--modify x and y and do other stuff

END LOOP;

Next Statement IF i < 0 THEN

NEXT;

END IF;

Others Clause WHEN OTHERS =>

--do some stuff

Package Declaration PACKAGE package_name IS

--declare some stuff

END PACKAGE;

Package Body PACKAGE BODY package_name IS

--put subprogram bodies here

END package_name;

Physical Type TYPE physical_type_name IS RANGE start TO end

UNITS

unit1 ;

unit2 = 10 unit1;

unit3 = 10 unit2;

END UNITS;

Port Clause PORT ( port1_name : port1_type; port2_name :

port2_type);

Port Map Clause PORT MAP (port1_name => signal1, signal2);

Procedure Declaration PROCEDURE procedure_name (parm1 : in

parm1_type; parm2 : out

parm2_type; parm3 :

inout parm3_type);

Procedure Body PROCEDURE procedure_name (parm1 : in

parm1_type; parm2 : out

parm1_type; parm3 :

inout parm3_type) IS

BEGIN

--do some stuff

END procedure_name;