28 Chapter Two
signal assignment statement creates a driver for signal a. The first state-
ment creates a driver that contains the value of signal bdelayed by 10
nanoseconds. The second statement creates a driver that contains the
value of signal cdelayed by 10 nanoseconds. How these two drivers are
resolved is left to the designer. The designers of VHDL did not want to
arbitrarily add language constraints to signal behavior. Synthesizing the
preceding example would short cand btogether.Bad Multiple Driver Model
Let’s look at a model that looks correct at first glance, but does not function
as the user intended. The model is for the 4 to 1 multiplexer discussed
earlier:USE WORK.std_logic_1164.ALL;
ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN std_logic;
PORT (q : OUT std_logic);
END mux;ARCHITECTURE bad OF mux IS
BEGIN
q <= i0 WHEN a = ‘ 0 ’ AND b = ‘ 0 ’ ELSE ‘ 0 ’;
q <= i1 WHEN a = ‘ 1 ’ AND b = ‘ 0 ’ ELSE ‘ 0 ’;
q <= i2 WHEN a = ‘ 0 ’ AND b = ‘ 1 ’ ELSE ‘ 0 ’;
q <= i3 WHEN a = ‘ 1 ’ AND b = ‘ 1 ’ ELSE ‘ 0 ’;
END BAD;This model assigns i0to qwhen ais equal to a 0 and bis equal to a 0;
i1when ais equal to a 1 and bis equal to a 0; and so on. At first glance,
the model looks like it works. However, each assignment to signal qcreates
a new driver for signal q. Four drivers to signal qare created by this model.
Each driver drives either the value of one of the i0, i1, i2, i3inputs
or ‘ 0 ’. The value driven is dependent on inputs aand b. If ais equal to
‘ 0 ’and bis equal to ‘ 0 ’, the first assignment statement puts the value
of i0into one of the drivers of q. The other three assignment statements
do not have their conditions met and, therefore, are driving the value ‘ 0 ’.
Three drivers are driving the value ‘ 0 ’, and one driver is driving the value
of i0. Typical resolution functions would have a difficult time predicting
the desired output on q, which is the value of i0.
A better way to write this model is to create only one driver for signal
q, as shown in the following: