and bound to an entity with a configuration. The component could have
been directly or implicitly configured.
In VHDL93 entities can be directly instantiated if they are visible. In
the example here entity adderfrom library work is directly instantiated
and configured in architecture struct.ENTITY direct IS
PORT( i1 : IN STD_LOGIC;
o1 : OUT STD_LOGIC);
END ENTITY direct;ARCHITECTURE struct OF direct IS
SIGNAL s1, s2 : STD_LOGIC;
BEGIN
U1 : ENTITY work.adder(behave)
GENERIC MAP(out_delay : delay_type)
PORT MAP(s1, s2, i1, o1);
END ARCHITECTURE struct;A separate configuration is not necessary as the entity is uniquely
specified. This makes it very easy to describe designs structurally and
with a lot less lines of VHDL code. However, it can make design reuse
more difficult.Extended Identifiers
In VHDL87 identifiers were limited to only characters a-z, A-Z, and 0-9.
This limited the number of identifiers that could be created. For manually
created VHDL this was not a major problem, but for VHDL that was
translated from some other format this caused some major problems.
Certain netlist formats contain identifiers that consist of operator symbols,
or start with a number. With VHDL93 the extended identifier allows the
user to specify identifiers in a much less restricted manner. Extended
identifiers can start with numbers or contain operator symbols.
Extended identifiers are specified by backslashes (\..\) around an
identifier. Extended identifiers can be used anywhere a normal identifier
can be used. An example using extended identifiers is shown here:entity \74ls163\ is
port (clk : in std_logic;
\1n1\ : in std_logic;
reset : in std_logic;
q1 : out std_logic;
q2 : out std_logic;
q3 : out std_logic);
end \74ls163\;Appendix D: VHDL93 Updates 453