VHDL Programming

These attributes act on both signals in the group.

Another way to describe a group, especially a group that varies in size,

is shown here:

GROUP timing_arc IS (SIGNAL <>);

This syntax is similar to an unconstrained array and describes a group

consisting of one or more signal objects.

Incremental Binding

In VHDL87 the rules about binding were very restrictive. If a component

was bound in a configuration specification, it could not be bound in a

configuration declaration. This made back-annotation of timing delays

rather difficult because the back annotation program had to generate not

only the generic parameter values, but also the proper entity use clauses.

What the modeler would like to do is pick the proper entity to use with a

configuration specification in the architecture of the containing entity,

and use a configuration declaration to specify the values for the back-

annotated timing.

In VHDL87 this was not possible because the component could be con-

figured in either place, but not both. In VHDL93 the incremental binding

feature allows the modeler to create models that behave as wanted.

An example is shown here:

ENTITY dff IS

GENERIC( delay : TIME;

PORT( din, clock : IN STD_LOGIC;

dout : OUT STD_LOGIC);

END ENTITY dff;

ENTITY top IS

PORT( z, clock : IN STD_LOGIC; qout : OUT STD_LOGIC);

END ENTITY top;

ARCHITECTURE struct OF top IS

COMPONENT dff IS

PORT( d, clk : IN STD_LOGIC;

q : OUT STD_LOGIC);

END COMPONENT dff;

FOR d1: dff USE ENTITY WORK.dff(behave)

GENERIC MAP (clk_to_q => 5.2 NS)

PORT MAP( d => din, clk => clock, q =>

open );

SIGNAL

458 Appendix D: VHDL93 Updates