VHDL Programming

(^470) Index
Composite type, 86– 96
Composite type resolution, 128– 130
Concurrent assignment problem,
67 – 69
Concurrent function, 110
Concurrent procedure, 110
Concurrent process statement, 41
Concurrent signal assignment, 5
Concurrent signal assignment
statement, 16
Conditional signal assignment, 436
Conditional signal assignment
statement, 18
Configuration declaration, 436
Configuration generic table, 195
Configuration statement, 11– 12
Configurations, 173– 204
architecture, 201– 203
block, 199– 201
board-socket-chip analogy,
195 – 199
component, 176– 183
default, 174– 176
defined, 2
entity-architecture pair
configuration, 180– 181
generic specifications, 190– 195
generic value specification, 188– 190
generics, 185– 188
lower-level, 179– 180
mapping library entities, 183– 185
port maps, 181– 183
power of, 12
Constants, 77– 78
Constraints, 237– 239
Control, 311– 321
Conversion functions, 113– 119
Copy (block copy operation), 299– 302
CPU, 289– 367
ALU, 306– 308
block copy operation, 299– 302
block diagram, 290, 304– 306
comp (comparation), 309– 311
control, 311– 321
debug, 401– 404
gate-level timing simulation,
379 – 398 (see alsoVITAL
simulation)
CPU (Cont.):
reg (address/instruction register),
321 – 322
regarray (storage registers),
322 – 323
RTL simulation, 329– 355
shift (shifting/rotation operations),
324 – 326
synthesis results, 357– 367
testbenches, 340–348. (See also
Testbenches)
top-level design, 293– 302
trireg (tristate register), 326– 328
Data types, 73– 108
access types, 96– 102
array types, 87– 93
composite types, 86– 96
enumerated types, 81– 84
file types, 102– 105
incomplete types, 98– 102
integer types, 80
overview (diagram), 79
physical types, 85– 86
real types, 81
record types, 93– 96
scalar types, 79– 86
subtypes, 105– 107
Deadlock, 64
DEALLOCATE, 96
Debugging (seeAt-Speed debugging)
Decimal integer literal, 443
Decimal real literal, 443
Decimal real with exponent, 443
Deferred constants, 78, 136– 137
Definitions, 2– 3
Delay, 20– 23
Delay constraints, 237– 239
DELAY_LENGTH, 452
Delay model, 242
'DELAYED, 161– 164
Delta delay evaluation mechanism, 26
Design under test (DUT), 330
DFF device, 388
Direct instantiation, 452– 453
Double-word instructions, 292
Drive, 240
Driver, 2, 27– 29