VHDL Programming

Index

Driver creation, 27

'DRIVING_VALUE, 450– 451

EDA Tool Settings Dialog box, 374,

376

8-bit lookahead adder, 249

8-bit ripple carry adder, 248

ELSE clause, 47, 48

ELSIF clause, 47, 48

End-of-file mark, 102

Entity, 2, 3– 4

Entity-architecture pair

configuration, 180– 186

Enumerated types, 81– 84

'EVENT, 157– 158

Event scheduling, 6

Exemplar Logic Leonardo Spectrum

synthesis tool, 231, 357

EXIT statement, 54– 56

Extended identifiers, 453

Factoring, 246

Fast testbench, 345– 348

Field Programmable Gate Array

(FPGA), 357

File, 102

File object declaration, 103

FILE_OPEN, 454– 455

File operations, 454– 455

FILE_STATUS, 454

File type declaration, 103

File types, 102– 105

Flattening, 245– 246

Flip-flop (VITAL model), 388– 392

FOR loop, 51, 52

FOREIGN, 456

Foreign interface, 455– 456

4-bit counter, 262

4-bit shifter, 264– 266

Four input mux symbol and function,

43

Four state truth table, 120

FPGA, 357

FPGA vendors, 284

Full testbench, 337– 340

Function array attributes, 154– 156

Function kind attributes, 151– 160

Function signal attributes, 156– 160

Function type attributes, 151– 154

Functional gate-level verification,

283 – 284

Functions, 110– 132

composite type resolution, 128– 130

conversion, 113– 119

nine-value resolution, 123– 128

pure/impure, 460

resolution, 119– 132

resolved signals, 130– 132

Gate level cells, 231

Gate level description, 236

Gate level netlist synthesis, 232

Gate level netlists, 231, 232

GENERATE statements, 220–224,

437, 456

Generic declaration, 437

Generic map, 437

Generic specifications, 190– 195

Generic value specification, 188– 190

Generics, 29– 31

Globally static assignment, 456– 457

Groups, 457– 458

Guarded blocks, 35– 37

Guarded signal assignment, 437

HDL debugger, 400

'HIGH, 144– 147

'HIGH(n), 154– 156

High-density design flow, 380

High-level design flow, 273– 287

design specification process, 273

functional gate-level verification,

283 – 284

overview (flowchart), 274

place and route, 284– 286

post layout timing simulation, 286

RTL simulation, 275– 277

static timing, 287

VHDL synthesis, 277– 283

Household alarm system, 253

Hybrid testbenches, 342– 345

Identifier, 81

IEEE 1076-1987 standard VHDL, 2

(see alsoVHDL 93 updates)

IEEE 1164 standard logic package,

413 – 433

471