30 Chapter Two
delays, as well as the loading that the device has on its output. With this
information, the model can correctly model the AND gate in the design.
Following is the architecture for the AND gate:ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal : BIT;
BEGIN
internal <= a AND b;
c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = ‘ 1 ’
ELSE internal AFTER (fall + (load * 3 ns));END load_dependent;The architecture declares a local signal called internalto store the
value of the expression aand b. Pre-computing values used in multiple
instances is a very efficient method for modeling.
The generics rise, fall, and loadcontain the values that were
passed in by the component instantiation statement. Let’s look at a
piece of a model that instantiates the components of type AND2in an-
other model:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY test IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT ( ina, inb, inc, ind : IN std_logic;
PORT ( out1, out2 : OUT std_logic);
END test;ARCHITECTURE test_arch OF test IS
COMPONENT AND2
GENERIC(rise, fall : TIME; load : INTEGER);
PORT ( a, b : IN std_logic;
PORT ( c : OUT std_logic);
END COMPONENT;
BEGIN
U1: AND2 GENERIC MAP(10 ns, 12 ns, 3 )
PORT MAP (ina, inb, out1 );U2: AND2 GENERIC MAP(9 ns, 11 ns, 5 )
PORT MAP (inc, ind, out2 );
END test_arch;The architecture statement first declares any components that will be
used in the model. In this example, component AND2is declared. Next, the
body of the architecture statement contains two of the component instan-
tiation statements for components U1and U2. Port aof component U1is
mapped to signal ina, port bis mapped to signal inb, and port cis mapped