VHDL Programming

(^474) Index
Sequential statements (Cont.):
EXIT statement, 54– 56
IF statement, 47– 48
LOOP statements, 50– 54
NEXT statement, 53– 54
VHDL synthesis, 257–259,
262 – 266
WAIT statements, 59– 66
SEVERITY clause, 57, 439
Severity level, 56– 57
Severity level error, 57
Severity level failure, 57
Shared variables, 461– 462
Shift instructions, 292
Shift operators, 463
Shifting operations, 324– 326
Side effects, 135
Signal assignment, 5, 72
Signal assignment statement, 5,
16 – 19
Signal kind attributes, 160– 169
Signals, 74– 76
Signals global to entities, 75– 76
Simple gate - concurrent assignment,
252 – 253
'SIMPLE_NAME, 451
Simulation
back-annotated, 397– 398
CPU, 349– 355
gate-level, 379– 398
post layout timing, 286
RTL, 275–277, 329– 355
VITAL, 379–398 (see alsoVITAL
simulation)
Simulation delta circuit, 24
Simulation deltas, 23– 27
Simulator-specific testbench,
340 – 342
Single-word instructions, 292
SLA (shift left arithmetic), 463
SLL (shift left logical), 463
SRA (shift right arithmetic), 463
SRL (shift right logical), 463
'STABLE, 164– 166
Stanculescu, Alec, 196
Standard delay format (SDF), 286
Standard library, 80
Standard logic package, 413– 433
Standard package, 80
State machine, 83– 84
State machine example (voicemail
controller), 266– 271
Statement concurrency, 6– 7
Statements/clauses, 435– 439
Static timing analyzer, 239, 287
Stimulus driver, 329, 330, 331
Stimulus only testbench, 333– 337
Storage registers, 322– 323
Store instructions, 291
String, 443
Structural architectures, 176
Structural designs, 7– 8
'STRUCTURE, 149– 151
Structuring, 246
Subprogram declaration, 137
Subprogram overloading, 206– 210
Subprogram parameter overloading,
208 – 210
Subprograms, 110– 135
functions, 110–132 (see also
Functions)
procedures, 133– 135
Subtypes, 105– 107
'SUCC, 151– 154
Syntax consistency, 464– 465
Synthesis, 243– 250
boolean optimization, 244
factoring, 246
flattening, 245– 246
mapping to gates, 247– 250
overview, 244
translation, 243
VHDL, 251–272 (see alsoVHDL
synthesis)
Synthesis tools, 11

T'BASE, 169– 170

T'HIGH, 144– 147

T'LEFT, 144– 147

T'LEFTOF, 151– 154

T'LOW, 144– 147

T'POS, 151– 154

T'PRED, 151– 154

T'RIGHT, 144– 147

T'RIGHTOF, 151– 154

T'SUCC, 151– 154