Index
Port maps, 181– 183
'POS, 151– 154
Post layout timing simulation, 286
Postponed process, 459– 460
'PRED, 151– 154
Predefined attributes, 143– 171
function array attributes, 154– 156
function kind attributes, 151– 160
function signal attributes, 156– 160
function type attributes, 151– 154
range kind attributes, 170– 171
signal kind attributes, 160– 169
type kind attributes, 169– 170
value array attributes, 147– 149
value block attributes, 149– 151
value kind attributes, 144– 151
value type attributes, 144– 147
Predefined physical types, 85– 86
preset, 261– 262
Primary design units, 3
Procedures, 133– 135
Process, 3
Process declarative part, 9, 41, 42
Process execution, 10
Process statement, 9–10, 40–42, 439
Pulse reject, 460– 461
Pure function, 460Qualified expressions, 215– 218
Quartus, 373
Quartus user interface, 373
Quick reference (seeVHDL reference
tables)
'QUIET, 166– 168'RANGE(n), 170– 171
Range kind attributes, 170– 171
Real types, 81
Record types, 93– 96
Reference tables (seeVHDL
reference tables)
Register and cloud diagram, 233
Register transfer level description,
232 – 237
Register Transfer Level (RTL) VHDL
description, 11
Registers
address, 321– 322Registers (Cont.):
instruction, 321– 322
storage, 322– 323
tristate, 326– 328
REPORT clause, 57, 439
REPORT statement, 461
Required time constraints, 238
reset, 260
Resolution functions, 27, 119– 132
Resolved signals, 130– 132
RETURN statement, 111, 439
'REVERSE_RANGE(n), 170– 171
'RIGHT, 144– 147
'RIGHT(n), 154– 156
'RIGHTOF, 151– 154
ROL (rotate left), 464
ROR (rotate right), 464
Rotate operators, 464
Rotating operations, 324– 326
RTL descriptions, 232– 237
RTL simulation, 275–277, 329– 355
CPU simulation, 349– 355
testbenches, 330–348 (see also
Testbenches)
RTL VHDL description, 11s'ACTIVE, 160
s'DELAYED, 161– 164
s'EVENT, 157– 158
s'LAST_ACTIVE, 160
s'LAST_EVENT, 158– 160
s'LAST_VALUE, 157– 158
s'QUIET, 166– 168
s'STABLE, 164– 166
s'TRANSACTION, 168– 169
Scalar types, 79– 86
Schematic Entry system, 31
SDF, 286
SDF file, 392– 394
Secondary design units, 3
Selected signal assignment, 19, 439
Sensitivity list, 40, 66
Sequential behavior, 8– 9
Sequential function, 110
Sequential procedure, 110
Sequential statements, 10, 46– 61
ASSERT statement, 56– 59
CASE statement, 48– 50473