32 Chapter Two
to logically group areas of the model. The analogy with a typical Schematic
Entry system is a schematic sheet. In a typical Schematic Entry system,
a level or a portion of the design can be represented by a number of
schematic sheets. The reason for partitioning the design may relate to
C design standards about how many components are allowed on a sheet,
or it may be a logical grouping that the designer finds more understandable.
The same analogy holds true for block statements. The statement area
in an architecture can be broken into a number of separate logical areas.
For instance, if you are designing a CPU, one block might be an ALU,
another a register bank, and another a shifter.
Each block represents a self-contained area of the model. Each block
can declare local signals, types, constants, and so on. Any object that can
be declared in the architecture declaration section can be declared in the
block declaration section. Following is an example:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE bit32 IS
TYPE tw32 IS ARRAY(31 DOWNTO 0) OF std_logic;
END bit32;LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.bit32.ALL;
ENTITY cpu IS
PORT( clk, interrupt : IN std_logic;
PORT( addr : OUT tw32; data : INOUT tw32 );
END cpu;ARCHITECTURE cpu_blk OF cpu IS
SIGNAL ibus, dbus : tw32;
BEGIN
ALU : BLOCK
SIGNAL qbus : tw32;
BEGIN
-- alu behavior statements
END BLOCK ALU;REG8 : BLOCK
SIGNAL zbus : tw32;
BEGIN
REG1: BLOCK
SIGNAL qbus : tw32;
BEGIN
-- reg1 behavioral statements
END BLOCK REG1;-- more REG8 statements