VHDL Programming

Behavioral Modeling 33

END BLOCK REG8;

END cpu_blk;

Entity cpuis the outermost entity declaration of this model. (This is

not a complete model, only a subset.) Entity cpudeclares four ports that

are used as the model interface. Ports clkand interruptare input ports,

addris an output port, and datais an inout port. All of these ports are

visible to any block declared in an architecture for this entity. The input

ports can be read from and the output ports can be assigned values.

Signals ibus and dbus are local signals declared in architecture

cpu_blk. These signals are local to architecture cpu_blkand cannot be

referenced outside of the architecture. However, any block inside of the

architecture can reference these signals. Any lower-level block can refer-

ence signals from a level above, but upper-level blocks cannot reference

lower-level local signals.

Signal qbusis declared in the block declaration section of block ALU.

This signal is local to block ALUand cannot be referenced outside of the

block. All of the statements inside of block ALUcan reference qbus, but

statements outside of block ALUcannot use qbus.

In exactly the same fashion, signal zbusis local to block REG8. Block

REG1inside of block REG8has access to signal zbus, and all of the other

statements in block REG8also have access to signal zbus.

In the declaration section for block REG1, another signal called qbusis

declared. This signal has the same name as the signal qbusdeclared in

block ALU. Doesn’t this cause a problem? To the compiler, these two signals

are separate, and this is a legal, although confusing, use of the language.

The two signals are declared in two separate declarative regions and are

valid only in those regions; therefore, they are considered to be two sep-

arate signals with the same name. Each qbuscan be referenced only in

the block that has the declaration of the signal, except as a fully qualified

name, discussed later in this section.

Another interesting case is shown here:

BLK1 : BLOCK

SIGNAL qbus : tw32;

BEGIN

BLK2 : BLOCK

SIGNAL qbus : tw32;

BEGIN

-- blk2 statements

END BLOCK BLK2;

-- blk1 statements