VHDL Programming

Sequential Processing 43

I0

I1

A B

Q

MUX4

ABQ

00I0

10I1

01I2

11I3

I3

I2

Figure 3-1
Four Input Mux Sym-
bol and Function.

Let’s look at two examples that illustrate this point more clearly. Both

examples are models of a 4 to 1 multiplexer device. The symbol and truth

table for this device are shown in Figure 3-1. One of the four input signals

is propagated to the output depending on the values of inputs A and B.

The first model for the multiplexer is an incorrect model, and the second

is a corrected version of the model.

Incorrect Mux Example

The incorrect model of the multiplexer has a flaw in it that causes the

model to produce incorrect results. This is shown by the following model:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY mux IS

PORT (i0, i1, i2, i3, a, b : IN std_logic;