44 Chapter Three
q : OUT std_logic);
END mux;ARCHITECTURE wrong of mux IS
SIGNAL muxval : INTEGER;
BEGIN
PROCESS ( i0, i1, i2, i3, a, b )
BEGIN
muxval <= 0;
IF (a = ‘ 1 ’) THEN
muxval <= muxval + 1;
END IF;IF (b = ‘ 1 ’) THEN
muxval <= muxval + 2;
END IF;CASE muxval IS
WHEN 0 =>
q <= I0 AFTER 10 ns;
WHEN 1 =>
q <= I1 AFTER 10 ns;
WHEN 2 =>
q <= I2 AFTER 10 ns;
WHEN 3 =>
q <= I3 AFTER 10 ns;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS;
END wrong;Whenever one of the input signals in the process sensitivity list changes
value, the sequential statements in the process are executed. The process
statement in the first example contains four sequential statements. Thefirst
statement initializes the local signalmuxvalto a known value (0). The sub-
sequent statements add values to the local signal depending on the value
of theaandbinput signals. Finally, the case statement chooses an input
to propagate to the output based on the value of signalmuxval. This model
has a significant flaw, however. The first statement:muxval <= 0;causes the value 0 to be scheduled as an event for signal muxval. In fact,
the value 0 is scheduled in an event for the next simulation delta because
no delay was specified. When the second statement:IF (a = ‘ 1 ’) THEN
muxval <= muxval + 1;
END IF;