VHDL Programming

Sequential Processing 61

q <= ‘ 0 ’;

ELSIF clock’EVENT AND clock = ‘ 1 ’ THEN

q <= d;

END IF;

WAIT ON reset, clock;

END PROCESS;

This process statement contains a WAIT ONstatement that causes the

process to halt execution until an event occurs on either resetor clock.

The IFstatement is then executed and, if resetis active, the flip-flop is

asynchronously reset; otherwise, the clock is checked for a rising edge

with which to transfer the dinput to the qoutput of the flip-flop.

A WAITstatement can also be used to control the signals a process or sub-

program is sensitive to at any point in the execution. Here is an example:

PROCESS

BEGIN

WAIT ON a; -- 1.

.

.

WAIT ON b; -- 2.

.

.

END PROCESS;

Execution of the statements in the PROCESSstatement proceeds until

point 1 in the VHDL fragment shown in the preceding. The WAITstate-

ment causes the process to halt execution at that point. The process does

not continue execution until an event occurs on signal a. The process is

therefore sensitive to changes in signal aat this point in the execution.

When an event occurs on signal a, execution starts again at the statement

directly after the WAITstatement at point 1. Execution proceeds until the

WAITstatement at point 2 is encountered. Once again, execution is halted,

and the process is now sensitive to events on signal b. Therefore, by

adding in two WAITstatements, we can alter the process sensitivity list

dynamically.

Next, let’s discuss the three different options available to the WAIT

statement:

WAIT ON signal [,signal]

WAIT UNTIL boolean_expression

WAIT FOR time_expression