VHDL Programming

(C. Jardin) #1

60 Chapter Three


WAITstatements can be used for a number of different purposes. The
most common use today is for specifying clock inputs to synthesis tools.
The WAITstatement specifies the clock for a process statement that is read
by synthesis tools to create sequential logic such as registers and flip-flops.
Other uses are to delay process execution for an amount of time or to
modify the sensitivity list of the process dynamically.
Let’s take a look at a process statement with an embedded WAITstate-
ment that is used to generate sequential logic:

PROCESS

BEGIN

WAIT UNTIL clock = ‘ 1 ’ AND clock’EVENT;
q <= d;
END PROCESS;

This process is used to generate a flip-flop that clocks the value of dinto
qwhen the clock input has a rising edge. The attribute ‘EVENTattached to
input clockis true whenever the clock input has had an event during the
current delta timepoint. (‘EVENTis discussed in great detail in Chapter 5.)
The combination of looking for a ‘ 1 ’value and a change on clockcreates
the necessary functionality to look for a rising edge on input clock. The
effect is that the process is held at the WAITstatement until the clock has
a rising edge. Then the current value of dis assigned to q.
Reading this description into a synthesis tool creates a D flip-flop
without a setor resetinput. A synchronous resetcan be created by
the following:

PROCESS

BEGIN

WAIT UNTIL clock = ‘ 1 ’ AND clock’EVENT;
IF (reset = ‘ 1 ’) THEN
q <= ‘ 0 ’;
ELSE
q <= d;
END IF;
END PROCESS;

When the clock occurs, the resetsignal is tested first. If it is active, then
the resetvalue (‘ 0 ’) is assigned to q; otherwise, the dinput is assigned.
Finally, an asynchronous resetcan be added as follows:

PROCESS

BEGIN

IF (reset = ‘ 1 ’) THEN
Free download pdf