VHDL Programming

(C. Jardin) #1

Sequential Processing 71


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END struct;

ARCHITECTURE switch OF dff IS
BEGIN
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END switch;

This example shows the entity for a D flip-flop with a passive process
included in the entity that performs a data setup check with respect to the
clock. This setup check function was described in detail in the ASSERTstate-
ment description. What this example shows is that, when the setup check
function is contained in the entity statement part, each of the architectures
for the entity have the data setup check performed automatically. With-
out this functionality, each of the architectures would have to have the
setup check code included. This introduces more code to maintain and can
introduce inconsistencies between architectures.
The only restriction on these processes, as mentioned earlier, is that
no signal assignment is allowed in a passive process. In the preceding ex-
ample, a process statement was used to illustrate a passive process. A pas-
sive process can also exist as a concurrent statement that does not do any
signal assignment. Examples of such statements are concurrent ASSERT
statements and concurrent subprogram invocations. An example of two
concurrent ASSERTstatements as passive processes are shown here:

ENTITY adder IS
PORT( A, B : IN INTEGER;
PORT( X : OUT INTEGER);
BEGIN
ASSERT (A < 256)
REPORT “A out of range”
SEVERITY ERROR;

ASSERT (B < 256)
REPORT “B out of range”
SEVERITY ERROR;

END adder;

The first ASSERTstatement checks to make sure that input Ais not out
of range, and the second assertion checks that input Bis not out of the
range of the adder. Each of these statements acts as an individual process
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