VHDL Programming

Data Types 75

USE IEEE.std_logic_1164.ALL;

ENTITY board_design is

PORT( data_in : IN bus_type;

PORT( data_out : OUT bus_type);

SIGNAL sys_clk : std_logic := ‘ 1 ’;

END board_design;

ARCHITECTURE data_flow OF board_design IS

SIGNAL int_bus : bus_type;

CONSTANT disconnect_value : bus_type

:= (‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’, ‘X’);

BEGIN

int_bus <= data_in WHEN sys_clk = ‘ 1 ’

ELSE int_bus;

data_out <= magic_function(int_bus) WHEN sys_clk = ‘ 0 ’

ELSE disconnect_value;

sys_clk <= NOT(sys_clk) after 50 ns;

END data_flow;

Signals vccand groundare declared in package sigdecl. Because

these signals are declared in a package, they can be referenced by more

than one entity and are therefore global signals. For an entity to refer-

ence these signals, the entity needs to use package sigdecl. To use the

package requires a VHDL USEclause, as shown here:

USE work.sigdecl.vcc;

USE work.sigdecl.ground;

Or:

USE work.sigdecl.ALL;

In the first example, the objects are included in the entity by specific

reference. In the second example, the entire package is included in the en-

tity. In the second example, problems may arise because more than what

is absolutely necessary is included. If more than one object of the same

name results because of the USEclause, none of the objects is visible, and a

compile operation that references the object fails.

SIGNALS GLOBAL TO ENTITIES Inside the entity declaration

section for entity board_designis a signal called sys_clk. This signal can

be referenced in entity board_designand any architecture for entity

board_design. In this example, there is only one architecture,data_flow,