Microsoft Word - Digital Logic Design v_4_6a

 In practice, most designs use crystal oscillators which oscillate at a precise frequency, providing

more reliable system clock.

 Design of Gated Sequential Logic Circuit
Providing another input which controls when the inputs can affect the outputs (latching the inputs)
increases the functionality of the latch circuit. The resulting circuit is called a latched or gated circuit.

 Gated Circuit Types

Latches may be classified based on their input control types:

 Level activated: Latches input when the control is at a given logic level (High or Low

depending on design)

 Edge Trigger: Latches input when the control changes level (rising- or falling-edge,

depending on design)

 Pulse-triggered: Latches input when the control is pulsed (a rising-edge followed by a falling-

edge)

 Gated S-R flip-flop (latch) Circuit

 This circuit allows inputs to affect the outputs only when C=1. When C=0, the latch holds the

last state value at its output. This is an example of high-level activated SR flip-flop.

∆t

(delay)

Q+

R

S

Q

Q’

(Not always shown)

C

S

C

R

Q

Q’

Block Diagram

Gated SR Latch Using NOR gates