Microsoft Word - Digital Logic Design v_4_6a

Symbols

Application: using D flip-flops with clear to build a shift register

 Edge-Triggered and Pulse-Triggered Flip Flop Comparison

A pulse enable the input to change the output. The pulse can be negative or positive

depending on the flip-flop design. Here is a comparison of hold time requirement for positive-

edge and positive-pulse triggered flip-flop.

• A pulse-triggered flip-flop has much longer sampling interval than an edge-triggered flip-
  flops; therefore, all new designs use Edge-triggered flip-flops to improve speed.

C

Positive-Edge

Triggered flip-

flop

C

Positive-Pulse

Triggered flip-

flop

tw = th

tsu th

tsi

ts = Set up time

th = Hold time

tw = Pulse width

tsi = Sampling interval = tsu + th

Shaded area is the area where

data must be stable.

D1 Q1

CLK

Clear’

D2 Q2

CLK

Clear’

D3 Q3

CLK

Clear’

D4 Q4

CLK

Clear’

CLOCK

Vcc

b0 (LSB) b1 b2 b3 (MSB)

Data

GND

CLK

DATA 1D

C1

Q

Q

Q

Q’

Positive-Edge-Triggered D Flip-Flop

(triangle called dynamic indicator)

CLK

DATA 1D

C1

Q

Q

Q

Q’

Negative-Edge-Triggered D Flip-Flop

(Bubbled triangle indicator)