Microsoft Word - Digital Logic Design v_4_6a

An alternative method is the use of Algorithmic State Machine (ASM) chart to describe the functionality.

 Analysis of JK Flip-Flop Circuits
Apply the 5-step FSM analysis to the following circuits:

1) Assign a present state variable to each flip flop in the synchronous system.

Yi representing flip-flop outputs for i = 1, 2, 3, ...

Solution: Refer to the schematics

2) Write the Excitation-input equation for JK flip-flop and the equation for the external-output.

3) Substitute the excitation-input equation into the characteristic equations for the flip-flops to

obtain the “next state” equations.

For J-K flip-flops  Yi+ = J i.Y i’ + K i’.Y i for i=1, 2, 3, ...

J 1 Q 1

K 1 Q 1 ’

C 1

System

Clock

J 2 Q 2

K 2 Q 2 ’

C 2

X Y^1 Y^2 Z^

00

X

01

X

11

X

10

X

(illegal

State)

(Reset

State)

0

0

0

0

1

1

1

1

Z

Mealy Output

Note: When Z is not shown, it is assumed the output is 0.