Microsoft Word - Digital Logic Design v_4_6a

 EXAMPLE - Design a 2-bit binary up-counter with a ripple carry output (RCO) using D flip-flops. The
input CLR’ is an asynchronous input that overrides the clock.

Step1) Design specifications using a timing diagram

**Notes:

1. T clk is the clock period and ST is the state time.


2. The first two events are less and then more than T clk.


3. Y1Y2 are the states (counts).


4. RCO is a Moore output indicating when the maximum count has been reached.

For completeness, we can also show the state diagrams. Although a timing diagram is more complete,
the state diagram is simpler to understand, since it does not contain the clock timing information.

Another way to show the functionality of this circuit is to use a PS/NS table.
Note: The ”Next state, NS” is the estate of the machine during the next clock cycle.

a

00, RCO’

d

11, RCO

b

01, RCO’

c

10, RCO’

State = Y 1 Y 2 ,Z

CLR’

CLK

CLR’

Y1 (msb)

Y2 (lsb)

RCO

a

ST > Tclk

c

ST < Tclk

Asynchronous Reset

b

ST = Tclk

c

ST = Tclk

d

ST = Tclk

a

ST = Tclk

b

ST = Tclk

Timing Events 1 2 3 4 5 6 7 8 9