All we need is the composite K-map for each of the desired outputs Y1+ ,Y2 +, Z:Step 5) Draw the Circuit Schematic A third application of the classical design process (using T flip-flop):
Design a synchronous sequential circuit identical to the previous example, except implement the
design using T flip-flops instead of D flip-flops.
Step1) Design Specifications using a Timing Diagram1D
Q
CLK
Q
R
1D
Q
CLK
Q
R
CLR’
SYS CLK
Y1
Y2
Y2’
D1
D2
Z
Y1’
00 0 1 1^
01
11
10
1 1 1
0 0 0
- - -
“-“ means don’t careY1Y2 Y1+ Y2 + Z
D1 = Y1+ = Y1’.Y2
D2 =Y2+ = Y1’
Z = Y1’
10 State is never reached.