Microsoft Word - Digital Logic Design v_4_6a

 74LS08 AND gate

tpcomb: Min at 3 ns and Max. at 18 ns

 75LS175 D-flip-flop

tpff: Min at 0 ns and Max. at 42 ns

tsu: Min at 20 ns

th: Min at 0 ns

 The fastest clock speed

TCLK(min) = tpff(max) + tpcomb(max) + tmarg) + tsu = 42 + 18 + 0 + 20 = 80 ns

FCLK(max) = 1/T CLK(min) = 1/80*10 -9 = 12.5 MHz

12.5 MHz is significantly slower than today’s technology, where the average personal

computer clock frequency is many GHz.

Example – Design
Design a system (Finite State Machine, FSM) that cycles through the following colors as shown
below:

Red Yellow Blue Black

White Green Violet Cyan

1D

Q

CLK

Q

R

1D

Q

CLK

Q

R

CLR’

SYS CLK

Y1

Y2

Y2’

D1

D2

Z

Y1’

tpcomb

tpff