Microsoft Word - Digital Logic Design v_4_6a

7.3. Introduction to Verilog HDL...........................................................................................................

The process of design is shared amongst the Hardware Description Languages (Verilog & VHDL) and
may be divided into front-end and backend as outlined below:

 The Front-end section is where all the decision are made and the design is documented.

 The Back-end section includes the implementation, and testing the product.

Although this process is iterative by its very nature, as the distance between the step that an error is
discovered and the step that the correction is made increases, the cost (time & resource) increases
exponentially.

Design can use only one or a combination of the following approaches (levels of abstraction) to describe
the design:

 Gate or Switch level

Design by describing the circuit in term of gates such as “and”, “or,” etc.

 Register-Transfer Level (RTL)

RTL describes the circuit using operations and the transfer of data between registers.

 Behavioral Level

At this level of abstraction, the circuit is described in a number of concurrent algorithms

describing the circuit behavior. This level of design is less hardware implementation specific.

Module is the basic block in Verilog. Before getting to language syntax and specifics, here is a example
code for a positive edge (rising edge) D Flip Flop. This is considered Behavioral-level design since we
are describing the behavior instead of specific gates (gate-level) or how the data flows amongst the
registers (RTL).

As always, start with a system diagram|

 Example – Verilog

Design a positive edge triggered D-FF using Verilog/

hierarchy/

block diagram

(Step 1)

coding

(Step 2)

compilation

(Step 3)

simulation/

verification

(Step 4)

timing

verification

(Step 7)

fiting/Place+

route

(Step 6)

Synthesis

(Step 5)

Design

Requirements

Back-end

Steps

Front-end

Steps