Microsoft Word - Digital Logic Design v_4_6a

change. in the following example the assignment is only triggered when the positive edge of clk is
encountered.

As you can see the assignment for q in the D flip flop example uses “<=” and not “=”. These two
assignment operators have distinct functionality:

 “=” is a blocking assignment and is used for combinational logic assignment. This operator
allows parallel assignment so anytime the expression changes, the output will change also.

 "<=" is a non-blocking assignment operator and is used for sequential logic. “<=” assignment
operator results in sequential execution (blocks concurrent execution).

The following two code segments and associated results shows the difference between the

“=” and “<=” operators

module Block_ex(clk);

input clk;

wire clk;

integer A=1, B=2, C=3;

always @ (posedge clk)

begin

A=4;

B=5;

C=A + B;

end

endmodule

module Non_Block_ex(clk);

input clk;

wire clk;

integer A=1, B=2, C=3;

always @ (posedge clk)

begin

A<=4;

B<=5;

C<=A + B;

end

endmodule

Results after 1 st execution C=3 Results after 1 st execution Results  C=9

`timescale 1ns/100ps // time unit is 1 ns with precision of 100 ps

// Design a D flip flop

// Author: Instructor

// Last Update: 6/5/2013

module D_ff(clock, d, q); // defines the input and output into module

input clock, d; // define input

wire clock, d; // declare input type

output q; // define output

reg q; // declare output

// Body of the design

always @ (posedge clock) // executes following code at every clock rising edge

begin

q <= d; // make an assignment

end

endmodule // end of module – note there is no ;