Microsoft Word - Digital Logic Design v_4_6a

 Example -

time thisTime; // declare thisTime to store time

Any of the types may be groups as arrays by adding by adding modifier [first:last]. you may use index to
refer to each of the array members. Remember, Verilog does not allow access to a range of array
members. In other word list[2:5] is a n illegal operation. Below are example of arrays:

 integer [1:20] grades; // integer type array with 21 element with first element at grades[1]

// and the last element at grades[20]

 real [0:30][0:90] gisCord; // You can even make a multi-dimension array by

// adding modifier [first][last] for each dimension.

Vectors is array of multiple bit types by adding modifier [msb:lbs]. For example:

 wire [15:0] exTest; // wire type with 16 bit with lsb at exTest[0] and msb at exTest[15]

 wire [-5:5] exTest; // wire type with 11 bit with msb at exTest[-5] and lsb at exTest[5]

 reg [13:-2] results; // reg type with 16 bits with lsb at results [-2] and msb at [13]

 reg signed [31:0] results; // reg type with 32 bits in 2’s complement.