Microsoft Word - Digital Logic Design v_4_6a

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Process runs until no other signal in the sensitivity list changes value as a result of running
the process.
 In simulation, all the statements in the process execute instantly (no elapsed time from start
to end of the process).

It is possible to write a process that never suspends. For example, a process with X in its sensitivity
list and containing the statement “X <= not X”. This process will never suspend will continuously
change. This is not a useful process and is similar to infinite loop. Most simulators will detect the
error and terminate after few thousand iterations.

Finally, the sensitivity list is optional; a process without a sensitivity list starts running at time zero in
simulation. One application of such a process is to generate an input waveform for the test bench.

 Example – Design a prime number detector using process-based data flow architecture.


architecture prime4_arch of prime is
begin
process(N)
variables N3L_N0, N3L_N2L_N1, N3L_N1_N0, N2_N1L_N0: STD_LOGIC;
begin
N3L_N0 := not N(3) and N(0);
N3L_N2L_N1 := not N(3) and not N(2) and N(1);
N3L_N1_N0 := not N(3) and not N(1) and N(0);
N2_N1L_N0 := N2 and not N(1) and N(0);
F <= N3L_N0 or N3L_N2L_N1 or N2L_N1_N0 or N2_N1L_N0;
end process
end prime4_arch;

Note: Within the prime4_arch we have only one concurrent statement and that is the process.

 Example – Design a Rising Edge D-Flip Flop.


entity ent_DFF is
begin
port(
D, clk, : in std_logic;
Q : out std_logic
);
end ent_DFF;

architecture arc_DFF of ent_DFF is
begin
pdf: process(clk)
begin
if (clk = ‘1’) then
q <= D;
end if;
end process pdf;
end arc_DFF;
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