Microsoft Word - Digital Logic Design v_4_6a

 PALs or GALs are named based on the number of inputs and outputs (PALxxyzz) where:

 “xx” is the number of maximum AND array inputs


 “y” represent the type of output

• Combination output: H is active High, L is active low, P is programmable


• Registered outputs: R is registered (Contains memory devices), RP is registered
  with programmable polarity.


• Versatile: V indicates programmable output macro-cells which can be configured to
  be either combinational or registered.
  
  “zz” represents the maximum number of dedicated outputs.

For example: PAL16L8 is active-Low output with 16 inputs and 8 outputs.

 PALs and GALs are programmed using Universal programmers which use JEDEC fuse map
file format. Some of the other names commonly used to refer to these devices based on their
complexity or size are:

 Simple Programmable Logic Devices (SPLD)

 Complex Programmable Logic Devices (CPLD)

 PAL usage example: Implement F(A 0 ,A 1 )= A 0 .A 1 +A 0 .A 1

Here again only one Fuse map is needed (AND array connection). Also need to consider if

there are any terms that can be shared. In this case we do not have any shared terms.

An ... A 0

p 0

p 1

p(2n+1-1)

n-bit input

Programmable AND array

...

p(2n+1)

OE 0

OE 1

..

Factory set

Intact Fuse