0195136047.pdf

292 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

an output and then go back to check it for self-consistency. This is given as a problem at the end

of the chapter. Figure 6.1.18 is a realization of an SRFF in terms of a physical circuit that behaves

similarly to the ideal device called SRFF which obeys theSRinstruction rules. Thus, note that

the circuit of Figure 6.1.18 cannot accurately be said to be an SRFF. While it is certainly possible

to apply the “forbidden” input (S= 1 andR= 1) to the real circuit, the circuit is then not properly

used as an SRFF.

Edge triggered SRFF symbols are illustrated in Figure 6.1.19. The triangle on the Ck (clock)

input indicates that the flip-flop is triggered on the edge of a clock pulse. Positive-edge triggering

is shown in Figure 6.1.19(a). Negative-edge triggering is indicated by the ring on the Ck input in

Figure 6.1.19(b).

DFLIP-FLOP(LATCH ORDELAYELEMENT)

The symbol for the clocked D flip-flop is shown in Figure 6.1.20(a), in which the two output

terminalsQandQ ̄behave just as in the SRFF, and the input terminals areDand Ck (clock). The

termclockedflip-flop indicates that this device cannot change its state (i.e.,Qcannot change)

unless a specific change instruction is given through the clock (Ck) input. The value ofQafter the

change instruction is equal to the value ofDat the time the change instruction is received. The

value ofQbefore the change instruction does not matter. Figure 6.1.20(b) illustrates the values

taken byQafter the change instruction for various inputsDand prior values ofQ. While there

are several variations of the device, in the rising-edge triggered flip-flop a change instruction is

effected whenever the Ck input makes a change from 0 to 1. Note that only a positive-going

transition of Ck is a change instruction, and a constant Ck input is not a change instruction.

Note that flip-flops havepropagation delay, which means that there is a small delay (about 20

ns) between the change instruction and the timeQactually changes. The value ofDthat matters

is its value when the change instruction is received, not its value at the later time whenQchanges.

A convenient means of describing the series of transitions that occur as the signals set to the

flip-flop input change is thetiming diagram. A timing diagram depicts inputs and outputs (as a

function of time) of the flip-flop (or any other logic device) showing the transitions that occur

over time. The timing diagram thus provides a convenient visual representation of the evolution

of the state of the flip-flop. However, the transitions can also be represented in tabular form.

Like logic blocks, flip-flops appear almost exclusively in IC form, and are more likely to be

found in LSI and VLSI form. A very important application is in computer memories, in which a

typical 256k RAM (random access memory) consists of about 256,000 flip-flops in a single IC.

S

Ck

Q

RQ

(a) (b)

S

Ck

Q

RQ

Figure 6.1.19Edge triggered SRFF symbols.

(a)Triggered on positive edge of clock pulse.

(b)Triggered on negative edge of clock pulse.

DQ

Ck Q

(a) (b)

D

0

0

1

1

Q(before) Q(after)

00

10

01

11

Figure 6.1.20Clocked D flip-flop.(a)Sym-

bol.(b)Qfor various inputsD.